The present invention relates to a metal oxide semiconductor transistor (MOS transistor) capable of applying to minute devices and a method of making the same, and more particularly to an improved MOS transistor and a method of making the same which can improve the characteristic of hot carrier and punch through.
As the technique of making semiconductor devices has been recently developed, the size of the semiconductor devices has been also reduced, thereby enabling the integration degree to be improved.
As the integration degree has been improved, the gate length of MOS transistors should be designed to have a value of from several microns to sub-micron.
If the length of the gate is shortened, the channel length of a MOS transistor is also shortened, thereby causing the effect of hot-carriers to occur.
Since the generated hot-carriers are trapped into a gate oxide film for insulating the gate and thus degrade the reliability of MOS transistor, the effect of hot-carriers has become a serious problem.
To solve the problem caused by the occurrence of hot-carriers, Lightly Doped Drain (LDD) MOS transistors having two kinds of source region and drain region have been proposed. That is, one of the two kinds is a low concentration of source region and drain region.
The other of two kinds is a high concentration of source region and drain region.
FIG. 1 illustrates a sectional view of a conventional LDD MOS transistor.
Referring to FIG. 1, a gate insulation film 12 is formed on a channel region 15 of a p-type silicon substrate 11 and a gate 13 made of a polysilicon film is formed on the gate insulation film 12.
Side wall spacers 14 made of an insulation film are formed at both side walls of the gate and n-type of source region 16 and drain region 17 having a low concentration are formed in the substrate 11 so that they are overlapped with the side wall spacers.
N-type of source region 18 and drain region 19 having a high concentration are formed in the substrate 11, adjacent to the n-type of source region 16 and drain region 17 having a low concentration, respectively.
This LDD MOS transistor can restrain the occurrence of hot-carriers due to the formation of n-type of source region 16 and drain region 17 having a low concentration, but can reduce the ON resistance of MOS transistors due to the parasitic resistance of n-type of source region 16 and drain region 17 having a low concentration.
Since the hot-carriers generated at the surface of the drain region 17 having a high concentration have a energy larger than thermal equilibrium state, the hot-carriers may be trapped in the side wall spacers 14 formed at both side walls of the gate 13.
Therefore, the drain characteristic of MOS transistors becomes degraded.
So as to solve the above-problem of LDD MOS transistors, an inverse T-shaped LDD structure has been proposed.
FIGS. 2a to 2f illustrate a method of making a conventional MOS transistor having an inverse T-shaped LDD.
Referring to FIG. 2a, a conventional field oxidation process is carried out on a p-type of silicon substrate 21 to form two field oxide films 22 for separating an active region 23 from adjacent others.
N-type of impurity ions having a low concentration are implanted into the silicon substrate 21 to form an n-type of impurity diffusion region 24 for a source region and a drain region having a low concentration.
Referring to FIG. 2b, a gate oxide film 25 is grown on an active region 23 of the silicon substrate 21 and a first polysilicon film 26 doped with impurity ions is deposited on the gate oxide film 25.
The impurity ions may be doped into the polysilicon film 26 during the deposition thereof or after the deposition thereof.
Subsequently, a phosphorous silicate glass (PSG) film 27 is deposited by a chemical vapor deposition process and then etched to form an opening 28.
Referring to FIG. 2c, an insulation film such as PSG is deposited and then etched-back to form spacers 29 at the side walls of the PSG film 27 located in the opening 28.
P-type of impurity ions are implanted into the silicon substrate 21 via the opening 28 using the PSG film 27 and spacers 29 as an ion-implantation mask, to form a p-type channel region 30. Therefore, n-type diffusion regions 24 adjacent to both sides of the channel region 30 become a source region and a drain region having a low concentration respectively.
Referring to FIG. 2d, a second polysilicon film 31 is formed to fill the opening 28.
An oxide film 32 is formed on the polysilicon film 31 by performing the thermal oxidation process on the polysilicon film.
Referring to FIG. 2e, the PSG film 27 and spacers 29 are all removed and spacers 33 made of an insulation film such oxide film are then formed at side walls of the second polysilicon film 31.
Accordingly, a portion of the first polysilicon film 26 is exposed.
Referring to FIG. 2f, the exposed portion of the first polysilicon film 26 is removed using the insulation film 32 and the spacers 33 as an etch mask.
Therefore, an inverse T shaped gate 34 is formed as shown in FIG. 2f.
The inverse T-shaped gate 34 is comprised of an upper portion made of the first polysilicon film 26 and a leg portion made of the second polysilicon film 31.
Subsequently, n.sup.+ -type of impurity ions are implanted, using the gate 34 and the spacers 33 as an ion-implantation mask, to form source and drain regions 35 having a high concentration.
Therefore, a MOS transistor having an LDD structure is obtained.
As above mentioned, this MOS transistor comprises an inverse T-shaped gate 34 including an upper portion made of the first polysilicon film 26 and a leg portion made of the second polysilicon film 31, n-type of source and drain regions 24 which are overlapped with the upper portion 26 and n.sup.+ -type of source and drain regions 35.
Herein, the above symbol (-) means a low concentration and the symbol (+) means a high concentration.
However, since the above method of making an inverse T shaped LDD MOS transistor carries out the above ion-implantation process over the whole action region to form a source region and a drain region having a low concentration, it is difficult to control the concentration of the channel region.
Since the p-type of channel region is formed under the gate to prevent the punch through, there is a disadvantage in that the threshold voltage is increased due to the back gate bias.
Since the thickness of the gate oxide film is also constant, the drain leakage may be induced due to the gate.
Another LDD MOS transistor called a double-implanted LDD MOS transistor has been proposed to improve the characteristic of punch through.
The double-implanted LDD MOS transistor (DI-LDD MOS transistor) has a structure in which the channel region is not formed under the gate but the p-type region for punch-through stop encloses the source region and drain region having low concentration.
FIGS. 3a to 3c illustrate a method of making a conventional DI-LDD MOS transistor.
Referring to FIG. 3a, a conventional field oxidation process is carried out on p-type of silicon substrate 41, to form a field oxide films 42 for separating an active region 43 from adjacent active regions.
Subsequently, a gate insulation film 44 is formed on the active region 43 of the substrate 41.
Subsequently, a polysilicon film is deposited on the whole surface of the substrate 41 and then patterned to form a gate 45.
N-type impurity ions such as phosphorous having a low concentration and p-type impurity ions such as boron are implanted into the substrate 41 using the gate 45 as an ion-implantation mask, respectively, and then annealed, to form a source region 46 and drain region 47 having low concentration and also a p-type of impurity region 48 for punch-through stop.
At this time, a p-type impurity region 48 is formed with a structure of pocket in which the p-type impurity region 48 encloses the source region 46 and drain region 47.
Referring to FIG. 3b, a CVD oxide film 49 is deposited on the whole surface of the substrate 41.
Referring to FIG. 3c, the CVD oxide film 49 is etched anisotropically to form spacers 50 at the side walls of the gate 45.
N.sup.+ -type of impurity ions such as phosphorous having a high concentration are implanted using the gate 45 and the spacers 50 as ion-implantation masks and then annealed to form a source region 51 and drain region 52 having a high concentration.
The p-type impurity region 48 is located such a method that it encloses the n-type of source region 46 and drain region 47 at the near location of the channel region.
Accordingly, since the DI-LDD MOS transistor encloses the n.sup.- -type of source region 46 and drain region 47, it is possible to reduce the short channel effect and the occurrence of hot carriers.
However, since the gate 45 is not completely overlapped with the n.sup.- -type of source region 46 and drain region 47, it is impossible to restrain the occurrence of hot carriers as above mentioned.
Since diffusing the implanted ions with the p-type impurity region 48 for punch-through stop is also formed by an annealing process, there is a limitation in that the p-type of impurity region 48 can not be defined deeply.